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high common-mode voltage, single-supply difference amplifier ad8202 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features high common-mode voltage range ?8 v to +28 v at a 5 v supply voltage operating temperature range: ?40c to +125c supply voltage range: 3.5 v to 12 v low-pass filter (1-pole or 2-pole) excellent ac and dc performance 1 mv voltage offset 1 ppm/c typical gain drift 80 db cmrr min dc to 10 khz applications transmission control diesel injection control engine management adaptive suspension control vehicle dynamics control general description the ad8202 is a single-supply difference amplifier for amplifying and low-pass filtering small differential voltages in the presence of a large common-mode voltage (cmv). the input cmv range extends from ?8 v to +28 v at a typical supply voltage of 5 v. the ad8202 is available in die and packaged form. the msop and soic packages are specified over a wide temperature range, from ?40c to +125c, making the ad8202 well-suited for use in many automotive platforms. automotive platforms demand precision components for better system control. the ad8202 provides excellent ac and dc performance keeping errors to a minimum in the users system. typical offset and gain drift in the soic package are 0.3 v/c and 1 ppm/c, respectively. typical offset and gain drift in the msop package are 2 v/c and 1 ppm/c, respec- tively. the device also delivers a minimum cmrr of 80 db from dc to 10 khz. the ad8202 features an externally accessible 100 k resistor at the output of the preamp a1 that can be used for low-pass filter applications and for establishing gains other than 20. functional block diagrams a1 +in ?in 200k 200k 100k a2 +in ?in g = 10 g = 2 ad8202 10k 10k +in ?in gnd out nc a1 a2 +v s nc = no connect 2 5 6 4 7 8 1 3 04981-001 figure 1. soic (r) package die form gnd nc ?in +in a1 +v s a2 out ad8202 5v output inductive load power device 4-term shunt clamp diode battery 14v common nc = no connect 04981-002 figure 2. high line current sensor gnd nc ?in +in a1 +v s a2 out ad8202 5v output inductive load power device 4-term shunt clamp diode battery 14v common nc = no connect 04981-003 figure 3. low line current sensor
ad8202 rev. d | page 2 of 20 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagrams............................................................. 1 specifications..................................................................................... 3 single supply ................................................................................. 3 absolute maximum ratings............................................................ 4 esd caution.................................................................................. 4 pin configuration and function descriptions............................. 5 typical performance characteristics ............................................. 6 theory of operation ...................................................................... 12 applications..................................................................................... 14 current sensing .......................................................................... 14 gain adjustment ........................................................................ 14 gain trim .................................................................................... 15 low-pass filtering...................................................................... 15 high line current sensing with lpf and gain adjustment 16 driving charge redistribution adcs..................................... 16 outline dimensions ....................................................................... 17 ordering guide .......................................................................... 17 revision history 11/05rev. c to rev. d updated format..................................................................universal changes to typical performance characteristics ........................ 6 added figure 18................................................................................ 8 added figure 25 to figure 27.......................................................... 9 added figure 32.............................................................................. 10 added figure 37 to figure 39........................................................ 11 changes to theory of operation.................................................. 12 added figure 41.............................................................................. 13 2/05rev. b to rev. c changes to table 1............................................................................ 3 changes to figure 14........................................................................ 8 changes to figure 22........................................................................ 9 1/05rev. a to rev. b changes to the general description.............................................. 1 changes to specifications ................................................................ 3 added figure 14 to figure 33.......................................................... 8 changes to figure 38...................................................................... 14 changes to figure 40 and figure 41............................................. 15 changes to ordering guide .......................................................... 16 11/04rev. 0 to rev. a changes to the features....................................................................1 changes to the general description...............................................1 changes to specifications (table 1) ................................................3 changes to absolute maximum ratings (table 2) .......................4 changes to pin function descriptions (table 3) ..........................5 changes to figure 5...........................................................................5 changes to figure 9 and figure 10..................................................6 updated outline dimensions....................................................... 12 changes to the ordering guide ................................................... 12 7/04revision 0: initial version
ad8202 rev. d | page 3 of 20 specifications single supply t a = operating temperature range, v s = 5 v, unless otherwise noted. table 1. ad8202 soic ad8202 msop ad8202 die parameter conditions min typ max min typ max min typ max unit system gain initial 20 20 20 v/v error 0.02 v out 4.8 v dc @ 25c ?0.3 +0.3 ?0.3 +0.3 % vs. temperature 1 20 1 25 1 30 ppm/c voltage offset input offset (rti) v cm = 0.15 v; 25c ?1 +1 ?2 +2 ?1 +1 mv vs. temperature ?40c to +125c ?10 +0.3 +10 ?20 +2 +20 ?10 +0.3 +10 v/c ?40c to +150c ?15 +5 +15 v/c input input impedance differential 260 325 390 260 325 390 260 325 390 k common mode 135 170 205 135 170 205 135 170 205 k cmv continuous ?8 +28 ?8 +28 ?8 +28 v cmrr 1 v cm = ?8 v to +28 v f = dc 82 82 82 db f = 1 khz 82 82 82 db f = 10 khz 2 80 80 80 db preamplifier gain 10 10 10 v/v gain error ?0.3 +0.3 ?0.3 +0.3 ?0.3 +0.3 % output voltage range 0.02 4.8 0.02 4.8 0.02 4.8 v output resistance 97 100 103 97 100 103 97 100 103 k output buffer gain 2 2 2 v/v gain error 0.02 v out 4.8 v dc ?0.3 +0.3 ?0.3 +0.3 ?0.3 +0.3 % output voltage range 0.02 4.8 0.02 4.8 0.02 4.8 v input bias current 40 40 40 na output resistance 2 2 2 dynamic response system bandwidth v in = 0.1 v p-p; v out = 2.0 v p-p 30 50 30 50 30 50 khz slew rate v in = 0.2 v dc; v out = 4 v step 0.28 0.28 0.28 v/s noise 0.1 hz to 10 hz 10 10 10 v p-p spectral density, 1 khz (rti) 275 275 275 nv/hz power supply operating range 3.5 12 3.5 12 3.5 12 v quiescent current vs. temperature v o = 0.1 v dc 0.25 1.0 0.25 1.0 0.25 1.0 ma psrr v s = 3.5 v to 12 v 75 83 75 83 75 83 db temperature range for specified performance ?40 +125 ?40 +125 ?40 +150 c 1 source imbalance <2 . 2 the ad8202 preamplifier exceeds 80 db cmrr at 10 khz. however, because the signal is available only by way of a 100 k resisto r, even the small amount of pin-to- pin capacitance between pin 1, pin 8 and pin 3, pin 4 might couple an input common-mode signal larger than the greatly attenuat ed preamplifier output. the effect of pin-to-pin coupling can be neglected in all applications by using filter capacitors at node 3.
ad8202 rev. d | page 4 of 20 absolute maximum ratings table 2. parameter rating supply voltage 12.5 v transient input voltage (400 ms) 44 v continuous input voltage (common mode) 35 v reversed supply voltage protection 0.3 v operating temperature range die ?40c to +150c soic ?40c to +125c msop ?40c to +125c storage temperature ?65c to +150c output short-circuit duration indefinite lead temperature range (soldering, 10 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality.
ad8202 rev. d | page 5 of 20 pin configuration and fu nction descriptions ?in 1 gnd 2 a1 3 a2 4 +in 8 nc 7 +v s 6 out 5 nc = no connect ad8202 top view (not to scale) 04981-004 figure 4. pin configuration table 3. pin function descriptions pin o. neonic 1 ?in ?409.0 ?205.2 2 gnd ?244.6 ?413.0 3 a1 +229.4 ?413.0 4 a2 +410.0 ?308.6 5 out +410.0 +272.4 6 +v s +121.0 +417.0 7 nc na na 8 +in ?409.0 +205.2 04981-005 1036 m +v s 1048 m a1 gnd out a2 +in ?in figure 5. metallization photograph
ad8202 rev. d | page 6 of 20 typical performance characteristics t a = 25c, v s = 5 v, v cm = 0 v, r l = 10 k, unless otherwise noted. frequency (hz) psrr (db) 90 70 80 50 60 40 10 20 30 0 10 100 1k 10k 100k 04981-006 figure 6. power supply rejection ratio vs. frequency valid for cm range ?8 v to +28 v frequency (hz) output (db) 30 25 20 15 5 10 0 100 1k 10k 100k 1m 04981-007 figure 7. bandwidth frequency (hz) cmrr (db) 100 95 90 85 75 80 70 10 100 1k 10k 100k 04981-008 figure 8. common-mode rejection ratio vs. frequency valid for common-mode range ?8 v to +28 v power supply (v) common-mode voltage (v) 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 3 4 5 6 7 8 9 10 11 12 13 04981-009 ?55 c ?40 c +25 c +125 c +150 c figure 9. negative common-mode voltage vs. voltage supply power supply (v) common-mode voltage (v) 40 35 25 30 20 5 10 15 0 36 5 48 71 0 91 1 12 04981-010 1 3 ?40 c ?55 c +25 c +125 c +150 c figure 10. positive common-mode voltage vs. voltage supply load resistance ( ) output swing (v) 5.0 4.0 4.5 3.5 3.0 2.5 0.5 1.0 1.5 2.0 0 10 100 1k 10k 04981-011 figure 11. output swing vs. load resistance
ad8202 rev. d | page 7 of 20 1 3 supply voltage (v) output minus supply (mv) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 36 5 48 71 0 91 11 2 04981-012 10k load no load figure 12. output minus supply vs. supply voltage 2 1 ch1 500mv 50mv m 20 s 2.5ms/s 400ns/pt a ch1 1.73v ch2 04981-013 output input figure 13. pulse response common-mode voltage (v) v os ( v) 1000 800 0 ?200 200 600 400 ?400 ?600 ?800 ?1000 ?10 ?5 10 5 02 0 15 30 04981-044 2 5 ?40 c +85 c +125 c +25 c figure 14. v os vs. common-mode voltage hits 18 12 14 16 10 8 6 4 2 0 cmrr ( v/v) ?70 ?65 ?60 ?45 ?55 ?50 ?40 ?35 ?30 ?25 ?20 ?10 ?15 ?5 0 5 10 15 20 30 25 35 40 45 50 55 65 60 70 04981-043 temperature = 25 c figure 15. cmrr distribution, ?8 v to +28 v common mode hits 8 7 6 5 4 3 2 1 0 v os drift ( v/c) ?28 ?26 ?24 ?22 ?20 ?18 ?16 ?14 ?12 ?10 ?6 ?8 ?4 ?2 0 2 4 6 8 10 12 14 18 16 20 22 24 28 26 04981-034 v supply = 5v temperature range = ?40 c to + 25 c figure 16. offset drif t distribution, msop, temperature range = ?40c to +25c hits 12 10 8 6 4 2 0 v os drift ( v/c) ?28 ?26 ?24 ?22 ?20 ?18 ?16 ?14 ?12 ?10 ?6 ?8 ?4 ?2 0 2 4 6 8 10 12 14 18 16 20 22 24 28 26 04981-036 v supply = 5v temperature range = 25 c to 125 c figure 17. offset drif t distribution, msop, temperature range = 25c to 125c
ad8202 rev. d | page 8 of 20 hits 10 9 8 7 5 4 3 2 1 6 0 v os drift ( v/c) ?16.0 ?14.0 ?12.0 ?10.0 ?8.0 ?6.0 ?4.0 ?2.0 0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 04981-052 v supply = 5v temperature range = 25 c to 85 c figure 18. offset drif t distribution, msop, temperature range = 25c to 85c hits 14 12 8 10 6 4 2 0 v os ( v) ?2200 ?2000 ?1800 ?1400 ?1600 ?1200 ?1000 ?800 ?600 ?400 ?200 200 400 600 1000 800 1200 1400 1600 1800 2000 2200 0 04981-037 temperature = 25 c figure 19. v os distribution, msop, temperature = 25c hits 10 8 7 9 4 6 3 5 1 2 0 v os ( v) ?2200 ?2000 ?1800 ?1400 ?1600 ?1200 ?1000 ?800 ?600 ?400 ?200 200 400 600 1000 800 1200 1400 1600 1800 2000 2200 0 04981-038 temperature = 125 c figure 20. v os distribution, msop, temperature = 125c hits 9 8 7 4 6 3 5 1 2 0 v os ( v) ?2200 ?2000 ?1800 ?1400 ?1600 ?1200 ?1000 ?800 ?600 ?400 ?200 200 400 600 1000 800 1200 1400 1600 1800 2000 2200 0 04981-039 temperature = ?40 c figure 21. v os distribution, msop, temperature = ?40c hits 14 12 10 8 6 4 2 0 error (%) ?0.15 ?0.13 ?0.11 ?0.07 ?0.09 ?0.05 ?0.03 ?0.01 0.01 0.05 0.03 0.07 0.09 0.11 0.13 0.17 0.15 0.19 0.21 0.23 0.27 0.25 0.29 04981-040 temperature = 25 c figure 22. msop gain accuracy, temperature = 25c hits 14 12 10 8 6 4 2 0 error (%) ?0.15 ?0.13 ?0.11 ?0.07 ?0.09 ?0.05 ?0.03 ?0.01 0.01 0.05 0.03 0.07 0.09 0.11 0.13 0.17 0.15 0.19 0.21 0.23 0.27 0.25 0.29 04981-041 temperature = 125 c figure 23. msop gain accuracy, temperature = 125c
ad8202 rev. d | page 9 of 20 hits 14 12 10 8 6 4 2 0 error (%) ?0.15 ?0.13 ?0.11 ?0.07 ?0.09 ?0.05 ?0.03 ?0.01 0.01 0.05 0.03 0.07 0.09 0.11 0.13 0.17 0.15 0.19 0.21 0.23 0.27 0.25 0.29 04981-042 temperature = ?40 c figure 24. msop gain accuracy, temperature = ?40c hits 9 8 7 6 5 4 3 2 1 0 gain drift (ppm/c) ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 12 10 14 16 18 04981-048 v supply = 5v temperature range = +25 c to ?40 c figure 25. gain drift distribution, msop, temperature range = +25c to ?40c hits 9 8 7 6 5 4 3 2 1 0 gain drift (ppm/c) ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 12 10 14 16 18 04981-049 v supply = 5v temperature range = 25 c to 85 c figure 26. gain drift distribution, msop, temperature range = 25c to 85c hits 10 8 9 7 6 5 4 3 2 1 0 gain drift (ppm/c) ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 12 10 14 16 18 04981-050 v supply = 5v temperature range = 25 c to 125 c figure 27. gain drift distribution, msop, temperature range = 25c to 125c hits 40 35 25 30 20 15 10 5 0 v os ( v) ?1500 ?1400 ?1300 ?1100 ?1200 ?1000 ?900 ?800 ?700 ?600 200 ?500 ?400 ?300 ?200 ?100 100 0 300 400 500 600 900 1200 1100 1400 1300 1000 1500 800 700 04981-028 temperature = 25 c figure 28. v os distribution, soic, temperature = 25c hits 30 25 20 15 10 5 0 v os ( v) ?1500 ?1400 ?1300 ?1100 ?1200 ?1000 ?900 ?800 ?700 ?600 200 ?500 ?400 ?300 ?200 ?100 100 0 300 400 500 600 900 1200 1100 1400 1300 1000 1500 800 700 04981-030 temperature = 125 c figure 29. v os distribution, soic, temperature = 125c
ad8202 rev. d | page 10 of 20 hits 35 25 30 20 15 10 5 0 v os ( v) ?1500 ?1400 ?1300 ?1100 ?1200 ?1000 ?900 ?800 ?700 ?600 200 ?500 ?400 ?300 ?200 ?100 100 0 300 400 500 600 900 1200 1100 1400 1300 1000 1500 800 700 04981-029 temperature = ?40 c figure 30. v os distribution, soic, temperature = ?40c hits 25 20 15 10 5 0 v os drift ( v/c) ?10.0 ?9.0 ?8.0 ?7.0 ?6.0 ?5.0 ?4.0 ?3.0 ?2.0 2.0 ?1.0 1.0 0 3.0 4.0 5.0 6.0 8.0 9.0 10.0 7.0 04981-025 v supply = 5v temperature range = ?40 c to + 25 c figure 31. offset drift distribution, soic, temperature range = ?40c to +25c hits 25 20 15 10 5 0 v os drift ( v/c) ?15.0 ?14.0 ?13.0 ?12.0 ?11.0 ?10.0 ?9.0 ?8.0 ?7.0 ?6.0 ?5.0 ?4.0 ?3.0 ?2.0 ?1.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 04981-051 v supply = 5v temperature range = 25 c to 85 c figure 32. offset drift distribution, soic, temperature range = 25c to 85c hits 30 25 20 15 10 5 0 v os drift ( v/ c) ?10.0 ?9.0 ?8.0 ?7.0 ?6.0 ?5.0 ?4.0 ?3.0 ?2.0 2.0 ?1.0 1.0 0 3.0 4.0 5.0 6.0 8.0 9.0 10.0 7.0 04981-027 v supply = 5v temperature range = 25 c to 125 c figure 33. offset drift distribution, soic, temperature range = 25c to 125c hits 40 35 30 25 20 15 10 5 0 error (%) 0 0.01 0.02 0.04 0.03 0.05 0.06 0.07 0.08 0.09 0.17 0.10 0.11 0.12 0.13 0.14 0.16 0.15 0.18 0.19 0.20 0.21 0.24 0.27 0.26 0.29 0.28 0.25 0.30 0.23 0.22 04981-031 temperature = 25 c figure 34. gain accuracy, soic, temperature = 25c hits 45 40 35 30 25 20 15 10 5 0 error (%) 0 0.01 0.02 0.04 0.03 0.05 0.06 0.07 0.08 0.09 0.17 0.10 0.11 0.12 0.13 0.14 0.16 0.15 0.18 0.19 0.20 0.21 0.24 0.27 0.26 0.29 0.28 0.25 0.30 0.23 0.22 04981-032 temperature = 125 c figure 35. gain accuracy, soic, temperature = 125c
ad8202 rev. d | page 11 of 20 hits 50 45 40 35 30 25 20 15 10 5 0 error (%) 0 0.01 0.02 0.04 0.03 0.05 0.06 0.07 0.08 0.09 0.17 0.10 0.11 0.12 0.13 0.14 0.16 0.15 0.18 0.19 0.20 0.21 0.24 0.27 0.26 0.29 0.28 0.25 0.30 0.23 0.22 04981-033 temperature = ?40 c figure 36. gain accuracy, soic, temperature = ?40c hits 40 35 30 20 25 15 10 5 0 gain drift (ppm/c) ?25 ?23 ?21 ?19 ?17 ?15 ?13 ?11 ?9 ?7 ?3 ?5 ?1 1 3 5 7 9 11 15 13 17 19 21 25 23 04981-045 v supply = 5v temperature range = + 25 c to ?40 c figure 37. gain drift distribution, soic, temperature range = +25c to ?40c hits 25 20 15 10 5 0 gain drift (ppm/c) ?25 ?23 ?21 ?19 ?17 ?15 ?13 ?11 ?9 ?7 ?3 ?5 ?1 1 3 5 7 9 11 15 13 17 19 21 25 23 04981-046 v supply = 5v temperature range = 25 c to 85 c figure 38. gain drift distribution, soic, temperature range = 25c to 85c hits 45 40 35 30 25 20 15 10 5 0 gain drift (ppm/c) ?25 ?23 ?21 ?19 ?17 ?15 ?13 ?11 ?9 ?7 ?3 ?5 ?1 1 3 5 7 9 11 15 13 17 19 21 25 23 04981-047 v supply = 5v temperature range = 25 c to 125 c figure 39. gain drift distribution, soic, temperature range = 25c to 125c
ad8202 rev. d | page 12 of 20 theory of operation the ad8202 consists of a preamp and buffer arranged as shown in figure 40 . like-named resistors have equal values. the preamp uses a dynamic bridge (subtractor) circuit. identical networks (within the shaded areas), consisting of r a , r b , r c , and r g , attenuate input signals applied to pin 1 and pin 8. when equal amplitude signals are asserted at input 1 and input 8, and the output of a1 is equal to the common potential (that is, 0), the two attenuators form a balanced-bridge network. when the bridge is balanced, the differential input voltage at a1, and thus its output, is 0. any common-mode voltage applied to both inputs keeps the bridge balanced and the a1 output at 0. because the resistor networks are carefully matched, the common-mode signal rejection approaches this ideal state. however, if the signals applied to the inputs differ, the result is a difference at the input to a1. a1 responds by adjusting its output to drive r b , by way of r g , to adjust the voltage at its inverting input until it matches the voltage at its noninverting input. by attenuating voltages at pin 1 and pin 8, the amplifier inputs are held within the power supply range, even if pin 1 and pin 8 input levels exceed the supply or fall below common (ground). the input network also attenuates normal (differential) mode voltages. r c and r g form an attenuator that scales a1 feedback, forcing large output signals to balance relatively small differen- tial inputs. the resistor ratios establish the preamp gain at 10. because the differential input signal is attenuated and then amplified to yield an overall gain of 10, amplifier a1 operates at a higher noise gain, multiplying deficiencies such as input offset voltage and noise with respect to pin 1 and pin 8. a1 a3 r cm r cm (trimmed) 100k r a ?in r g r c r b r a r c r b r g +in com a2 r f r f ad8202 5 4 3 1 2 8 04981-014 figure 40. simpli fied schematic to minimize these errors while extending the common-mode range, a dedicated feedback loop is used to reduce the range of common-mode voltage applied to a1 for a given overall range at the inputs. by offsetting the voltage range applied to the com- pensator, the input common-mode range is also offset to include voltages more negative than the power supply. amplifier a3 detects the common-mode signal applied to a1 and adjusts the voltage on the matched r cm resistors to reduce the common-mode voltage range at the a1 inputs. by adjusting the common voltage of these resistors, the common-mode input range is extended while, at the same time, the normal mode signal attenuation is reduced, leading to better performance referred to input. the output of the dynamic bridge taken from a1 is connected to pin 3 by way of a 100 k series resistor, provided for low- pass filtering and gain adjustment. the resistors in the input networks of the preamp and the buffer feedback resistors are ratio-trimmed for high accuracy. the output of the preamp drives a gain-of-2 buffer amplifier, a2, implemented with carefully matched feedback resistors (r f ). the 2-stage system architecture of the ad8202 enables the user to incorporate a low-pass filter prior to the output buffer. by separating the gain into two stages, a full-scale, rail-to-rail signal from the preamp can be filtered at pin 3, and a half-scale signal, resulting from filtering, can be restored to full scale by the output buffer amp. the source resistance seen by the inverting input of a2 is approximately 100 k to minimize the effects of the input bias current of a2. however, this current is quite small, and errors resulting from applications that mismatch the resistance are correspondingly small. the a2 input bias current has a typical value of 40 na, however, this can increase under certain conditions. for example, if the input signal to the a2 amplifier is v cc /2, the output attempts to go to v cc due to the gain of 2. however, the output saturates because the maximum specified voltage for correct operation is 200 mv below v cc . under these conditions the total input bias current increases (see figure 41 for more information).
ad8202 rev. d | page 13 of 20 ?140 0 0 2.5 04981-053 differential-mode voltage (v) a2 input bias current (na) ?120 ?100 ?80 ?60 ?40 ?20 0.5 1.0 1.5 2.0 v supply = 5v temperature range = +1 25 c to ?40 c figure 41. a2 input bias current vs. input voltage and temperature. the shaded area is the bias current from +125c to ?40c. an increase in the a2 bias current, in addition to the output saturation voltage of a1, directly affects the output voltage of the ad8202 system (pin 3 and pin 4 shorted). an example of how to calculate the correct output voltage swing of the ad8202, by taking all variables into account, follows: ? amplifier a1 output saturation potential can drop as low as 20 mv at its output. ? a2 typical input bias current of 40 na multiplied by the 100 k preamplifier output resistor produces 40 na 100 k = 4 mv at the a2 input ? total voltage at the a2 input equals the output saturation voltage of a1 combined with the voltage error generated by the input bias current 20 mv + 4 mv = 24 mv ? the total error at the input of a2, 24 mv, multiplied by the buffer gain generates a result ing error of 48 mv at the output of the buffer. this is ad8202 system output low saturation potential. ? the high output voltage rang e of the ad8202 is specified as 4.8 v. therefore, assuming a typical a2 input bias current, the output voltage range for the ad8202 is 48 mv to 4.8 v. for an example of the effect of changes in a2 input bias current vs. applied input potentials, see figure 41 . the change in bias current causes a change in erro r voltage at the input of the buffer amplifier. this results in a change in overall error potential at the output of the buffer amplifier.
ad8202 rev. d | page 14 of 20 applications the ad8202 difference amplifier is intended for applications that require extracting a small differential signal in the presence of large common-mode voltages. the differential input resistance is nominally 325 k, and the device can tolerate common-mode voltages higher than the supply voltage and lower than ground. the open collector output stage sources current to within 20 mv of ground and to within 200 mv of v s . current sensing high line, high current sensing basic automotive applications using the large common-mode range are shown in figure 2 and figure 3 . the capability of the device to operate as an amplifier in primary battery supply circuits is shown in figure 2 ; figure 3 illustrates the ability of the device to withstand voltages below system ground. low current sensing the ad8202 is also used in low current sensing applications, such as the 4 to 20 ma current loop shown in figure 42 . in such applications, the relatively large shunt resistor can degrade the common-mode rejection. adding a resistor of equal value on the low impedance side of the input corrects for this error. 5v output 10 1% 10 1% nc = no connect + gnd nc ?in +in a1 +v s a2 out ad8202 04981-015 figure 42. 4 to 20 ma current loop receiver gain adjustment the default gain of the preamplifier and buffer are 10 and 2, respectively, resulting in a composite gain of 20. with the addition of external resistor(s) or trimmer(s), the gain can be lowered, raised, or finely calibrated. gains less than 20 because the preamplifier has an output resistance of 100 k, an external resistor connected from pin 3 and pin 4 to gnd decreases the gain by a factor r ext /(100 k + r ext ) as shown in figure 43 . 10k 10k 100k a2a1 gnd ?in out +v s nc+in ad8202 out +v s r ext v cm v diff 2 gain = 20r ext r ext + 100k r ext = 100k gain 20 ? gain v diff 2 nc = no connect 04981-016 figure 43. adjusting for gains less than 20 the overall bandwidth is unaffected by changes in gain by using this method, although there may be a small offset voltage due to the imbalance in source resistances at the input to the buffer. this can often be ignored, but if desired, it can be nulled by inserting a resistor equal to 100 k minus the parallel sum of r ext and 100 k, in series with pin 4. for example, with r ext = 100 k (yielding a composite gain of 10), the optional offset nulling resistor is 50 k. gains greater than 20 connecting a resistor from the output of the buffer amplifier to its noninverting input, as shown in figure 44 , increases the gain. the gain is multiplied by the factor r ext /(r ext ? 100 k); for example, the gain is doubled for r ext = 200 k. overall gains as high as 50 are achievable in this way. the accuracy of the gain becomes critically dependent on the resistor value at high gains. also, the effective input offset voltage at pin 1 and pin 8 (about six times the actual offset of a1) limits the parts use in high gain, dc-coupled applications. 10k 10k 100k a2a1 gnd ?in out +v s nc+in ad8202 out +v s r ext v cm v diff 2 gain = 20r ext r ext ? 100k r ext = 100k gain gain ? 20 v diff 2 nc = no connect 04981-017 figure 44. adjusting for gains > 20
ad8202 rev. d | page 15 of 20 gain trim figure 45 shows a method for incremental gain trimming by using a trim potentiometer and external resistor, r ext . the following approximation is useful for small gain ranges: g (10 m/ r ext )% thus, the adjustment range is 2% for r ext = 5 m; 10% for r ext = 1 m, and so on. 5v out r ext gain trim 20k min v cm v diff 2 v diff 2 nc = no connect gnd nc ?in +in a1 +v s a2 out ad8202 04981-018 figure 45. incremental gain trim internal signal overload considerations when configuring gain for values other than 20, the maxi- mum input voltage with respect to the supply voltage and ground must be considered because either the preamplifier or the output buffer reaches its full-scale output (approximately v s ? 0.2 v) with large differential input voltages. the input of the ad8202 is limited to (v s ? 0.2)/10 for overall gains 10 because the preamplifier, with its fixed gain of 10, reaches its full- scale output before the output buffer. for gains greater than 10, the swing at the buffer output reaches its full scale first and limits the ad8202 input to (v s ? 0.2)/g, where g is the overall gain. low-pass filtering in many transducer applications, it is necessary to filter the signal to remove spurious high frequency components including noise, or to extract the mean value of a fluctuating signal with a peak-to-average ratio (par) greater than unity. for example, a full-wave rectified sinusoid has a par of 1.57, a raised cosine has a par of 2, and a half-wave sinusoid has a par of 3.14. signals having large spikes can have pars of 10 or more. when implementing a filter, the par should be considered so that the output of the ad8202 preamplifier (a1) does not clip before a2 because this nonlinearity would be averaged and appear as an error at the output. to avoid this error, both amplifiers should clip at the same time. this condition is achieved when the par is no greater than the gain of the second amplifier (2 for the default configuration). for example, if a par of 5 is expected, the gain of a2 should be increased to 5. low-pass filters can be implemented in several ways by using the ad8202. in the simplest case, a single-pole filter (20 db/decade) is formed when the output of a1 is connected to the input of a2 via the internal 100 k resistor by tying pin 3 and pin 4 and adding a capacitor from this node to ground, as shown in figure 46 . if a resistor is added across the capacitor to lower the gain, the corner frequency increases; it should be calculated using the parallel sum of the resistor and 100 k. 5v v cm v diff 2 v diff 2 nc = no connect c gnd nc ?in +in a1 +v s a2 out ad8202 04981-019 output f c = 1 2 c10 5 c in farads figure 46. single-pole, low-pass filter using the internal 100 k resistor if the gain is raised using a resistor, as shown in figure 44 , the corner frequency is lowered by the same factor as the gain is raised. thus, using a resistor of 200 k (for which the gain would be doubled), the corner frequency is now 0.796 hz/f (0.039 f for a 20 hz corner frequency). 5v v cm v diff 2 v diff 2 nc = no connect c gnd nc ?in +in a1 +v s a2 out ad8202 04981-020 out c 255k f c (hz) = 1/c( f) figure 47. 2-pole, low-pass filter a 2-pole filter (with a roll-off of 40 db/decade) can be implemented using the connections shown in figure 47 . this is a sallen-key form based on a 2 amplifier. it is useful to remember that a 2-pole filter with a corner frequency f 2 and a 1-pole filter with a corner at f 1 have the same attenuation at the frequency (f 2 2 /f 1 ). the attenuation at that frequency is 40 log (f 2 /f 1 ), which is illustrated in figure 48 . using the standard resistor value shown and equal capacitors (see figure 47 ), the corner frequency is conveniently scaled at 1 hz/f (0.05 f for a 20 hz corner). a maximally flat response occurs when the resistor is lowered to 196 k and the scaling is then 1.145 hz/f. the output offset is raised by approximately 5 mv (equivalent to 250 v at the input pins).
ad8202 rev. d | page 16 of 20 40log (f 2 /f 1 ) f 1 attenuation f 2 f 2 2 /f 1 frequency a 1-pole filter, corner f 1 , and a 2-pole filter, corner f 2 , have the same attenuation ?40log (f 2 /f 1 ) at frequency f 2 2 /f 1 20db/decade 40db/decade 04981-021 figure 48. comparative responses of 1-pole and 2-pole low-pass filters high line current sensing with lpf and gain adjustment figure 49 is another refinement of figure 2 , including gain adjustment and low-pass filtering. gnd nc ?in +in a1 +v s a2 out ad8202 5v inductive load power device 4-term shunt clamp diode batter y 14v nc = no connect common 04981-022 c out 4v/amp 5% calibration range f c (hz) = 0.796hz/c( f) (0.22 f for f c = 3.6hz) v os/ib null 191k 20k figure 49. high line current sensor interface; gain = 40, single-pole, low-pass filter a power device that is either on or off controls the current in the load. the average current is proportional to the duty cycle of the input pulse and is sensed by a small value resistor. the average differential voltage across the shunt is typically 100 mv, although its peak value is higher by an amount that depends on the inductance of the load and the control frequency. the common-mode voltage, conversely, extends from roughly 1 v above ground for the on condition to about 1.5 v above the battery voltage in the off condition. the conduction of the clamping diode regulates the common-mode potential applied to the device. for example, a battery spike of 20 v can result in an applied common-mode potential of 21.5 v to the input of the devices. to produce a full-scale output of 4 v, a gain 40 is used, adjustable by 5% to absorb the tolerance in the shunt. sufficient headroom allows 10% overrange (to 4.4 v). the roughly triangular voltage across the sense resistor is averaged by a 1-pole low-pass filter, set with a corner frequency of 3.6 hz, providing about 30 db of attenuation at 100 hz. a higher rate of attenuation can be obtained using a 2-pole filter with f c = 20 hz, as shown in figure 50 . although this circuit uses two separate capacitors, the total capacitance is less than half that needed for the 1-pole filter. gnd nc ?in +in a1 +v s a2 out ad8202 5v inductive load power device 4-term shunt clamp diode battery 14v nc = no connect common 04981-023 f c (hz) = 1/c( f) (0.05 f for f c = 20hz) c output 127k c 432k 50k figure 50. 2-pole low-pass filter driving charge redistribution adcs when driving cmos adcs, such as those embedded in popular microcontrollers, the charge injection (q) can cause a significant deflection in the output voltage of the ad8202. though generally of short duration, this deflection can persist until after the sample period of the adc expires due to the relatively high open-loop output impedance (typically 21 k) of the ad8202. including an r-c network in the output can significantly reduce the effect. the capacitor helps to absorb the transient charge, effectively lowering the high frequency output impedance of the ad8202. for these applications, the output signal should be taken from the midpoint of the r lag ? c lag combination, as shown in figure 51 . because the perturbations from the analog-to-digital converter are small, the output impedance of the ad8202 appears to be low. the transient response, therefore, has a time constant governed by the product of the two lag components, c lag r lag . for the values shown in figure 51 , this time constant is programmed at approximately 10 s. therefore, if samples are taken at several tenths of microseconds or more, there is negligible charge stack-up. +in ?in 10k 10k ad8202 5v r lag 1k c lag 0.01 f microprocessor a/d a2 2 4 6 5 04981-024 figure 51. recommended circuit for driving cmos a/d
ad8202 rev. d | page 17 of 20 outline dimensions 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012-aa figure 52. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) compliant to jedec standards mo-187-aa 0.80 0.60 0.40 8 0 4 8 1 5 pin 1 0.65 bsc seating plane 0.38 0.22 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.08 3.20 3.00 2.80 5.15 4.90 4.65 0.15 0.00 0.95 0.85 0.75 figure 53. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters ordering guide model temperature range package description package option branding ad8202yr ?40c to +125c 8 lead standard small outline package [soic_n] r-8 ad8202yr-reel ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ad8202yr-reel7 ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ad8202yrz 1 ?40c to +125c 8 lead standard small outline package [soic_n] r-8 ad8202yrz-rl 1 ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ad8202yrz-r7 1 ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ad8202yrmz 1 ?40c to +125c 8-lead mini small outline package [msop] rm-8 jwy ad8202yrmz-rl 1 ?40c to +125c 8-lead mini small outline package [msop] rm-8 jwy ad8202yrmz-r7 1 ?40c to +125c 8-lead mini small outline package [msop] rm-8 jwy ad8202ycsurf die 1 z = pb-free part.
ad8202 rev. d | page 18 of 20 notes
ad8202 rev. d | page 19 of 20 notes
ad8202 rev. d | page 20 of 20 notes ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04981-0-11/05(d)

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